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| d a t a sh eet product speci?cation supersedes data of 1997 oct 03 file under integrated circuits, ic01 1998 mar 13 integrated circuits saa7710t dolby* pro logic surround; incredible sound
1998 mar 13 2 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t features two stereo i 2 s-bus digital input channels three stereo i 2 s-bus digital output channels i 2 c-bus mode control up to 45 ms on-chip delay-line (f s = 44.1 khz) optional clock divider for crystal oscillator package: so32l operating supply voltage range: 4.5 to 5.5 v. functions 4-channel active surround, 20 hz to 20 khz (maximum 1 2 f s ) adaptive matrix 7 khz low-pass filters adjustable delay for surround channel modified dolby b noise reduction noise sequencer variable output matrix sub woofer centre mode control: on/off, normal, phantom, wide output volume control automatic balance and master level control with dc-offset filter hall/matrix surround sound functions incredible sound functions 5-band parametric equalizer on main channels left, centre, right (f s = 32 khz) tone control (bass/treble) on all four output channels (f s = 44.1 khz). general description this data sheet describes the 104 rom-code version of the saa7710t chip. the saa7710t chip is a high quality audio-performance digital add-on processor for digital sound systems. it provides all the necessary features for complete dolby pro logic surround sound on chip. in addition to the dolby pro logic surround function, this device also incorporates a 5-band parametric equalizer, a tone control section and a volume control. instead of dolby pro logic surround, the hall/matrix surround and incredible sound functions can be used together with the equalizer or tone control. quick reference data remark dolby*: dolby and pro logic are trademarks of dolby laboratories licensing corporation. they are available only to licensees of dolby laboratories licensing corporation, san francisco, ca94111, usa, from whom licensing and application information must be obtained. ordering information symbol parameter min. max. unit v dd dc supply voltage - 0.5 +6.5 v d v dd voltage difference between two v ddx pins - 550 mv v i maximum input voltage - 0.5 v dd + 0.5 v i dd dc supply current - 50 ma i ss dc supply current - 50 ma t amb ambient operating temperature - 40 +85 c t stg storage temperature range - 65 +150 c type number package name description version saa7710t/n104 so32 plastic small outline package; 32 leads; body width 7.5 mm sot287-1 1998 mar 13 3 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram handbook, full pagewidth mge751 dolby pro logic or dolby 3 stereo or hall/matrix or incredible sound surround channel delay line i 2 s input switch circuit auto balance function 5-band parametric equalizer or tone control sw c r l variable output matrix i 2 s out 1 i 2 s out 2 i 2 s out 3 i 2 c bus transceiver oscillator flag test control test 22 23 24 25 27 26 data 1 17 13 3 rtcb tscan dsp_reset i 2 s_wsin2 i 2 s_bckin2 i 2 s_datain2 i 2 s_datain1 i 2 s_wsin1 i 2 s input 1 i 2 s_bckin1 + + 7 8 9 10 15 16 14 21 20 4 dsp_in1 dsp_in2 dsp_out1 dsp_out2 sda scl a0 osc xtal shtcb 2 1 28 29 30 5 12 32 19 18 6 11 31 v ss3 v ss2 v ss1 v ss_xtal v dd_xtal v dd3 v dd2 v dd1 i 2 s_dataout3 i 2 s_dataout2 i 2 s_dataout1 i 2 s_wsout i 2 s_bckout s saa7710t i 2 s outputs i 2 s input 2 fig.1 block diagram. 1998 mar 13 4 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t pinning symbol pin description i 2 s_wsout 1 i 2 s-bus slave word-select output i 2 s_bckout 2 i 2 s-bus slave bit-clock output r tcb 3 asynchronous reset test control block input (active low) shtcb 4 clock divider switch enable input (low = divide) v dd1 5 positive power supply v ss1 6 ground power supply dsp_in1 7 ?ag input 1 dsp_in2 8 ?ag input 2 dsp_out1 9 ?ag output 1 dsp_out2 10 ?ag output 2 v ss2 11 ground power supply v dd2 12 positive power supply tscan 13 scan control input a0 14 i 2 c-bus slave address selection input sda 15 i 2 c-bus serial data input/output scl 16 i 2 c-bus serial clock input dsp_reset 17 chip reset input (active low) v ss_xtal 18 ground power supply crystal oscillator v dd_xtal 19 positive power supply crystal oscillator xtal 20 crystal oscillator output osc 21 crystal oscillator input i 2 s_bckin1 22 i 2 s-bus master bit-clock input 1 i 2 s_wsin1 23 i 2 s-bus master word-select input 1 i 2 s_datain1 24 i 2 s-bus master data input 1 i 2 s_datain2 25 i 2 s-bus master data input 2 i 2 s_wsin2 26 i 2 s-bus master word-select input 2 i 2 s_bckin2 27 i 2 s-bus master bit-clock input 2 i 2 s_dataout1 28 i 2 s-bus slave data output 1 i 2 s_dataout2 29 i 2 s-bus slave data output 2 i 2 s_dataout3 30 i 2 s-bus slave data output 3 v ss3 31 ground power supply v dd3 32 positive power supply fig.2 pin configuration. handbook, halfpage saa7710t mge750 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 i 2 s_wsout i 2 s_bckout rtcb shtcb v dd1 v ss1 dsp_in1 dsp_in2 dsp_out1 dsp_out2 v ss2 v dd2 tscan a0 v dd3 v ss3 i 2 s_dataout3 i 2 s_dataout2 i 2 s_bckin2 i 2 s_wsin2 i 2 s_dataout1 i 2 s_datain2 i 2 s_datain1 i 2 s_wsin1 i 2 s_bckin1 osc xtal v dd_xtal sda scl v ss_xtal dsp_reset 1998 mar 13 5 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t functional description figure 1 shows the block diagram of the saa7710t. the saa7710t consists of a dolby pro logic decoder together with equalizer or tone control. the dolby pro logic part of the ic may be used to decode audio soundtracks (dolby surround movies or dolby surround video productions) from for example, a video recorder (vcr) or a cd laser disc into four channels left, centre, right and surround (l, c, r and s). if desired, post-processing with either an equalizer or a tone control section is possible. in addition to this, a sub woofer (sw) channel, digital volume control and a user-programmable variable output matrix are implemented. hall/matrix surround sound functions are implemented for material not encoded using dolby surround. these features can be used as an alternative to dolby pro logic and can also be combined with the equalizer or tone control sections. incredible sound is a philips patented technology which substantially improves the stereo effect of a television or audio system. using advanced signal processing, speakers that are positioned close together can imitate the sound produced by speakers that are far apart. functional modes the device thus supports three main modes, dolby pro logic/dolby 3 stereo or hall/matrix surround or incredible sound mode. all modes can be combined with equalizing (3-band or 5-band) or tone control depending on f s and available cycle budget. t he d olby p ro l ogic mode in dolby pro logic mode, several blocks must be initialized and controlled during operation: noise generator and noise sequencer centre channel mode (1) (normal, phantom, wide, off) combining network coefficients 7 khz low-pass filter in surround channel (1) surround channel delay time (1) modified dolby b noise reduction must be on. possible post-processing modes for dolby pro logic are: volume control only (1) the coef?cient set used to initialize and control the operation of the dolby pro logic mode depends upon the selected sampling frequency f s = 32, 44.1 or 48 khz. equalizer (3- or 5-band on l, c and r) or tone control (l, c, r and s); fixed output matrix (1) ; volume control equalizer (5-band on l, c and r); variable output matrix (1) ; volume control extra sub woofer (1) . t he d olby 3 stereo mode in dolby 3 stereo mode, several blocks must be initialized and controlled during operation: noise generator and noise sequencer centre channel mode (1) (normal, phantom, wide and off) combining network coefficients incredible sound widening of the stereo base on two speakers effect is user adjustable. t he hall / matrix surround mode in hall/matrix surround mode, the blocks listed below must be initialized and controlled during operation: input balance control hall or matrix surround mode setting all-pass and filter transfer characteristics (1) 7 khz low-pass filter in surround channel (1) surround channel delay (1) . possible post-processing modes for hall/matrix surround are as above: volume control only equalizer (5-band on l, c and r) or tone control (l, c, r and s); fixed output matrix (1) ; volume control equalizer (5-band on l,c,r); variable output matrix (1) ; volume control extra sub woofer (1) . t he incredible sound mode in the incredible sound mode the blocks listed below must be initialized and controlled during operation: incredible sound coefficients combining network coefficients. possible post-processing modes for incredible sound are as follows: volume control only equalizer (5-band on l and r) or tone control (l and r); variable output matrix (1) , volume control extra sub-woofer (1) . 1998 mar 13 6 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t a dditional information the possible modes of operation are discussed in more detail in the saa7710t dolby pro logic programming guide, application note an95063 . this also includes which features are available for a given system clock frequency and sample frequency and the possible input configurations. clock circuit and oscillator the chip has an on board crystal clock oscillator. the block schematic of this pierce oscillator is shown in figs 3 and 4. the active element needed to compensate for the loss resistance of the crystal is the amplifier gm. this amplifier is placed between the xtal (output) pin and the osc (sense) pin. the gain of the oscillator is internally controlled by the automatic gain control. this prevents too much power loss in the crystal. the higher harmonics are then as low as possible. the signals on the osc and xtal pin are differentially amplified. the oscillator has these two modes of operation: the crystal oscillator mode: in this mode (see fig.3), a quartz crystal oscillator is used to generate a clock signal which is subsequently divided by 2 to ensure that the final clock signal has a 50% duty cycle. the oscillator circuit components r bias and c1, c2 depend on the crystal. in the case of an overtone oscillator, the ground harmonic is filtered out by l1 and c3. pin shtcb is held low so that the divided signal is selected. only a quartz crystal should be used in this mode. the slave oscillator mode: in this mode (see fig.4), the oscillator circuit acts as a slave driven by a master system clock. the clock divider can be switched on or off using pin shtcb. when the divider is not used, the duty cycle of the clock will depend on the master system clock duty cycle and the rising and falling edge times. this places a tolerance of 5% on the 50% duty cycle of the master system clock (see chapter ac characteristics). in order to be able to control the phase of the clock signal during testing the divider is skipped and the signal is directly fed to the circuit via the multiplexer in the test position. s upply of the crystal oscillator the power supply connections to the oscillator are separated from the other supply lines to minimise feedback from on-chip ground bounce to the oscillator circuit. noise on the power supply affects the agc operation so the power supply should be decoupled. the v ss_xtal pin is used as ground supply and the v dd_xtal as positive supply. 1998 mar 13 7 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t fig.3 block diagram crystal oscillator circuit. handbook, full pagewidth mge752 clock buffer test shtcb = 0 xtal r bias 100 k w v dd_xtal v ss_xtal off chip on chip 4 18 19 20 osc c1 10 pf c2 10 pf c3 1 nf 21 0 1 divide by 2 gm l1 4.7 m h agc fig.4 block diagram slave oscillator circuit. handbook, full pagewidth mge753 clock buffer shtcb = 1 xtal 100 k w v dd_xtal v ss_xtal off chip on chip 4 18 19 20 osc 10 pf slave input 10 nf 40 pf 21 divide by 2 gm agc test 0 1 1998 mar 13 8 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t i 2 s-bus interfaces and system clock i 2 s- bus basics fig.5 i 2 s-bus timing and format. handbook, full pagewidth t cy t lc 3 0.35 t t sr 3 0.2 t t hr 3 0 t hc 3 0.35 t v ih (70%) v il (20%) v ih (70%) v il (20%) sck mbh173 sd sck ws sd ws msb right msb left for communication with external digital sources and or additional external processors the i 2 s-bus digital interface bus is used. it is a serial 3-line bus, with one line for data, one line for clock and one line for the word select. figure 5 shows an excerpt of the philips i 2 s-bus specification interface report regarding the general timing and format of i 2 s-bus. word select (ws) logic 0 means left channel word, logic 1 means right channel word. the serial data is transmitted in twos complement with the msb first. one clock period after the negative edge of the word select line the msb of the left channel is transmitted. data is synchronised with the negative edge of the clock and latched at the positive edge. i 2 s- bus input circuit the i 2 s-bus input circuits can be configured in the following way using the sel-in1/in2 bit (see table 4): 1. i 2 s input 1 is master (sel-in1/in2 bit = logic 0(default)) 2. i 2 s input 2 is master (sel-in1/in2 bit = logic 1). the incoming bit-clock frequency defines the accuracy in terms of number of bits of the incoming data samples. the input circuit is designed to accept any number of bits per channel up to a maximum of 18 bits. the accepted data format is msb-first. 1998 mar 13 9 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t table 1 data accuracy in i 2 s-bus interface incoming data width i 2 s-bus in data width i 2 s-bus out data width a<18 a a b 3 18 18 18 t he i 2 s- bus output interface the i 2 s-bus data output interfaces (see fig.1) i 2 s out 1, i 2 s out 2 and i 2 s out 3 use the same i 2 s-bus data signals which are selected by the input switch circuit. the i 2 s-bus ws and bck output signals remain in phase with the external input signals at all times. the output data is 1/f s cycle delayed relative to the input data. the selected word-select and bit-clock are included as part of the output interface: i 2 s_wsout, i 2 s_bckout. these two output signals can be 3-stated by setting the dis_bckws bit (see table 4). the 3-state output of the i 2 s_dataout3 signal can be enabled by setting the ena_i 2 s3 bit (see table 4). the timing diagram of the i 2 s-bus outputs is shown in fig.6. the timing details can be found in chapter ac characteristics. fig.6 timing diagram of i 2 s-bus output interface. handbook, full pagewidth mge755 t hc t lc t d1 t f t r t f t r t d3 t f t r t s2 t d2 t acc cl ws data (in) data (out) data valid msb msb i 2 s_bckin1, 2 i 2 s_bckout i 2 s_wsin1, 2 i 2 s_wsout i 2 s_datain1, 2 i 2 s_dataout1, 2, 3 1998 mar 13 10 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t i 2 c-bus control and commands c haracteristics of the i 2 c- bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to the v ddx via a pull-up resistor when connected to the output stages of a microprocessor. data transfer can only be initiated when the bus is not busy. b it transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. the maximum clock frequency is 100 khz (see fig.7). start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see fig.8). d ata transfer a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see fig.9). a cknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse, set up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition (see fig.10). fig.7 bit transfer on the i 2 c-bus. handbook, full pagewidth mlc160 sda scl data line stable data valid change of data allowed 1998 mar 13 11 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t fig.8 start and stop conditions. a ndbook, full pagewidth mlc161 sda scl s p start condition stop condition fig.9 data transfer on the i 2 c-bus. handbook, full pagewidth mlc162 sda scl s p start condition stop condition 1 2 7 8 9 1 2 3 to 8 9 msb ack acknowledgement signal from receiver byte complete interrupt within receiver clock line held low while interrupts are serviced acknowledgement signal from receiver 1998 mar 13 12 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t fig.10 acknowledge on the i 2 c-bus. handbook, full pagewidth mlc163 data output from receiver scl from master s start condition 12 789 clock pulse for acknowledgement acknowledge not acknowledge data output from transmitter i 2 c- bus format addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with the first byte transmitted after the start procedure. slave address (pin a0) the chip acts as a slave receiver or a slave transmitter. therefore the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the chip slave address is shown in table 2. the sub address bit a0 corresponds to the hardware address pin a0 which allows the device to have 1 of 2 different addresses. write cycles the i 2 c-bus configuration for a write cycle is shown in fig 12. the write cycle is used to write in the input selector control register and to initialise or update coefficient values. the data length is 2 bytes or 3 bytes depending of the accessed memory. if the y-memory is addressed the data length is 2 bytes, in case of the x-memory the length is 3 bytes. the slave receiver detects the address and adjusts the bytes accordingly. read cycles the i 2 c-bus configuration for a read cycle is shown in fig 13. the read cycle is used to read data values from xram or yram. 1998 mar 13 13 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t i 2 c- bus function bits input selector control register the write only, two byte, input selector control register is located on absolute address 0fffh (4095) and consists of 16 bits, starting with bit 0 and ending with bit 15. deviation from the i 2 c-bus speci?cation 1. the data hold time (t hd;dat ) for this device ( 3 0 ns as stated in the i 2 c-bus specification) should be as follows: a) for the crystal oscillator mode ( shtcb = 0): 3 b) for the slave oscillator mode ( shtcb = 0): 3 c) for the slave oscillator mode ( shtcb = 1): 3 6 f xtal --------- ? ?? 6 f slave ------------- ? ?? 3 f slave ------------- ? ?? during the write cycle, the i 2 c-bus clock frequency must be reduced. the i 2 c-bus clock frequency has the following constraints: f s > 2 f iic f s =i 2 s-bus sampling frequency f iic =i 2 c-bus clock frequency. if this constraint cannot be met, a higher i 2 c-bus frequency can be obtained in the following way: by making the i 2 c-bus master insert a delay (t d ) after the acknowledge pulse (see fig.11). the delay should be larger than or equal to 1/f s where f s is the i 2 s-bus sampling frequency. by not using the auto-increment feature. this means that each data word must be preceded by its intended destination address. fig.11 timing of reduced i 2 c-bus frequency. handbook, full pagewidth mge756 acknowledge after word t d auto-increment address register scl sda 1998 mar 13 14 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t table 2 slave address table 3 location of input selector control register bits in i 2 c-bus serial transmission; note 1 note 1. explanation for the contents of the register bits: a) a = standard i 2 c-bus acknowledge. b) number = bit number according to table 4. c) p = standard i 2 c-bus stop condition. table 4 input selector control bits xram format the xram block consists of 256 18-bit ram locations 0 to 255 and is located on the absolute address range of 0000h to 00ffh. the i 2 c-bus transfer consists of 18 useful bits out of 24 bits. table 5 format xram bits; note 1 note 1. explanation for the contents of the register bits: a) d = contents of i 2 c-bus data register bit is dont care. b) a = standard i 2 c-bus acknowledge. c) number = bit number being useful bit xram memory. d) p = standard i 2 c-bus stop condition. msb lsb 001111a0r/ w msb lsb datah datal 15141312111098a76543210ap symbol function number of bits on reset bit no sel-in1/in2 i 2 s input 1 or i 2 s input 2 input 1 in1(0) 5 dis_bckws disable i 2 s_bckout and i 2 s_wsout 1 enable(0) 7 ena-i 2 s3 enable i 2 s_dataout3 1 disable(0) 13 imode i ?ag resets/background tasking 1 resets(0) 15 msb lsb datah datam datal dddddd1716a1514131211109 8 a 76543210ap 1998 mar 13 15 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t yram format the yram block consists of 256 12-bit ram locations 0 to 255 and is located on the absolute address range of 0800h to 08ffh. the i 2 c-bus transfer consists of 12 useful bits out of 16 bits. table 6 format yram bits; note 1 note 1. explanation for the contents of the register bits: a) d = contents of i 2 c-bus data register bit is dont care. b) a = standard i 2 c-bus acknowledge. c) number = bit number being useful bit xram memory. d) p = standard i 2 c-bus stop condition. error processing if a read action is done without first initialising the memory address the acknowledge after the read command will not be generated by the chip. this should be treated as an error message: table 7 msb lsb datah datam dddd111098a76543210ap s write ack addrh ack addrl ack s read correct read sequence s read neg ack incorrect read sequence; address is not initialized 1998 mar 13 16 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 01111a 0 0 a c k a c k a c k a c k a c k address s 0 addr h addr l data h data m r/w mbh529 auto increment if repeated n-groups of 3 (2) bytes p a c k data l fig.12 master transmitter writes to chip. 01111a 0 0 a c k a c k a c k a c k a c k address s 0 011 1 11a 0 s 0 addr h addr l data h r/w mbh528 auto increment if repeated n-groups of 3 (2) bytes p a c k a c k data m data l r/w fig.13 master transmitter reads from chip. 1998 mar 13 17 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t dsp_reset the dsp_reset pin is active low and has an internal pull-up resistor. to enable a proper switch-on of the supply voltage a capacitor should be connected between this pin and v ss . the capacitor value is such that the chip is in a reset state as long as the power supply is not stabilized. the dsp_reset has the following functions: the bits of the input selector control register are set to logic 0 (see table 4) the program counter is set to address 0000h the i 2 c-bus interface is initialised; the sda pin is guaranteed high-impedance. when the level on the dsp_reset pin is high, the dsp program starts to run. when the level on the dsp_reset pin is low, the sda pin is asynchronously set to a high-impedance state. in the absence of a clock and during the power-up reset, the sda line is high-impedance. t est mode connections (tscan, r tcb and shtcb pins ) the tscan, rtcb and shtcb pins are used to put the chip in test mode and to test the internal connections. each pin has an internal pull-down resistor to ground. in the application these pins can be left open-circuit or connected to ground. limiting values in accordance with the absolute maximum rating system (iec134). thermal characteristics symbol parameter conditions min. max. unit v dd dc supply voltage - 0.5 +6.5 v d v dd voltage difference between two v ddx pins - 550 mv v i(max) maximum input voltage - 0.5 v dd + 0.5 v l ik dc input clamp diode current v i < - 0.5 v or v i >v dd + 0.5 v - 10 ma l ok dc output clamp diode current output type 4 ma v o < - 0.5 v or v o >v dd + 0.5 v - 20 ma l o dc output source or sink current output type 4 ma - 0.5v 1998 mar 13 19 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t ac characteristics v dd1 =v dd2 =v dd3 =v dd_xtal = 4.5 to 5.5 v; t amb =25 c; unless otherwise speci?ed. notes 1. the load capacitance is the sum of the series connection of c1 and c2 (see fig.3) and the parasitic parallel capacitor of the crystal c p . 2. with a 50%, 5% duty cycle on oscillator drive input (see fig.4). 3. the value for the capitative load c l is given in pf. symbol parameter conditions min. typ. max. unit f xtal crystal frequency see fig.3 -- 36.864 mhz a f spurious frequency attenuation 20 -- db i xtal current through crystal at input voltage swing 0.2 v - 500 -m a g m(xtal) transconductance at start-up 4 8 - ms v xtal voltage across crystal note 1 - 500 - mv c l(xtal) load capacitance - 25 - pf r xtal allowed loss resistor of crystal c p = 5 pf; c1 = 10 pf; c2 = 10 pf - 20 60 w slave oscillator f slave slave frequency no divider; see fig.4 -- 18.432 mhz slvolt slave drive voltage see fig.4 3.75 -- v t r input rise times 0.1 to 0.9v dd_xtal ; note 2 -- 20 ns t f input fall times 0.1 to 0.9v dd_xtal ; note 2 -- 20 ns timing i 2 c- bus inputs / output t f fall time i 2 c-bus 0.1 to 0.9v dd - 5.7 - ns f i(max) maximum input frequency sda, scl -- 100 khz i 2 s- bus inputs / outputs t r rise time i 2 s-bus (o2) c l = 30 pf; 0.1 to 0.9v dd - 7.3 - ns t f fall time i 2 s-bus (o2) c l = 30 pf; 0.1 to 0.9v dd - 8.3 - ns t hc cl pulse width high 112 -- ns t lc cl pulse width low 112 -- ns t d1 ws out delay time 0 -- ns t d2 data in hold time 0 -- ns t s2 data in set-up time 25 -- ns t d3 data out delay time 0 - 5ns t acc data out access time -- 5 + 0.5 c l (3) ns all other outputs (o1) t r rise time c l = 30 pf; 0.1 to 0.9v dd - 7.3 - ns t f fall time c l = 30 pf; 0.1 to 0.9v dd - 8.3 - ns all other i nputs t r input rise times v dd = 5.5 v - 6 200 ns t f input fall times v dd = 5.5 v - 6 200 ns 1998 mar 13 20 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t internal circuitry pin symbol pin type dc voltage (v) internal circuit 7 dsp_in1 i1 8 dsp_in2 i1 16 scl i1 22 i 2 s_bckin1 i1 23 i 2 s_wsin1 i1 24 i 2 s_datain1 i1 25 i 2 s_datain2 i1 26 i 2 s_wsin2 i1 27 i 2 s_bckin2 i1 17 dsp_reset i4 3 r tcb i2 4 shtcb i2 13 tscan i2 14 a0 i1 1i 2 s_wsout o2 2i 2 s_bckout o2 9 dsp_out1 o2 30 i 2 s_dataout3 o2 mge758 7, 8, 16, 22, 23, 24, 25, 26, 27 mge759 17 + mge760 3, 4, 13, 14 mge761 1, 2, 9, 30 1998 mar 13 21 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t 15 sda i3 10 dsp_out2 o1 28 i 2 s_dataout1 o1 29 i 2 s_dataout2 o1 5v dd1 tbf 6v ss1 0 11 v ss2 0 12 v dd2 5 31 v ss3 0 32 v dd3 5 21 osc tbf 20 xtal tbf 19 v dd_xtal 5 18 v ss_xtal 0 pin symbol pin type dc voltage (v) internal circuit mge762 15 mge763 10, 28, 29 mge764 19 21 20 18 1998 mar 13 22 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... application information handbook, full pagewidth mge757 100 k w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 4.7 m h 10 k w 220 w 220 w 100 nf 100 nf 100 nf 100 nf 100 m f (6.3 v) 100 m f (6.3 v) 220 pf 100 pf 100 pf 10 pf 10 pf 1 nf 220 pf 220 pf 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 w 220 pf 220 pf 220 pf 220 pf 220 pf 220 pf 470 pf 220 pf dolby pro logic or dolby 3 stereo or hall/matrix or incredible sound surround channel delay line auto balance function 5-band parametric equalizer or tone control sw c r l variable output matrix i 2 s out 1 i 2 s out 2 i 2 s out 3 i 2 c bus transceiver oscillator flag test control test 13 17 26 27 25 24 23 22 3 rtcb tscan dsp_reset 220 pf + + 7 8 9 10 15 16 14 21 20 4 dsp_in1 dsp_in2 dsp_out1 dsp_out2 sda scl a0 + 5 v + 5 v + 5 v 10 k w + 5 v osc xtal shtcb 2 1 28 29 30 5 12 32 19 18 6 11 31 v ss3 v ss2 v ss1 v ss_xtal v dd_xtal v dd3 v dd2 v dd1 i 2 s_dataout3 i 2 s_wsin2 i 2 s_bckin2 i 2 s_wsin1 i 2 s input 1 i 2 s outputs i 2 s_bckin1 i 2 s_datain2 i 2 s_datain1 i 2 s_dataout2 i 2 s_dataout1 i 2 s_wsout i 2 s_bckout blm32a07 blm32a07 s saa7710t i 2 s input switch circuit data 1 i 2 s input 2 fig.14 application diagram. 1998 mar 13 23 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.10 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot287-1 (1) 0.012 0.004 0.096 0.086 0.02 0.01 0.050 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w m b p d h e z e c v m a x a y 32 17 16 1 q a a 1 a 2 l p q detail x l (a ) 3 e pin 1 index 0 5 10 mm scale so32: plastic small outline package; 32 leads; body width 7.5 mm sot287-1 95-01-25 97-05-22 1998 mar 13 24 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1998 mar 13 25 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 1998 mar 13 26 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t notes 1998 mar 13 27 philips semiconductors product speci?cation dolby* pro logic surround; incredible sound saa7710t notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca57 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 545102/1200/04/pp28 date of release: 1998 mar 13 document order number: 9397 750 03268 |
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